View TPS54372PWPRG4_9066797.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features description applications tps54372 slvs430d ? june 2002 ? revised february 2005 3-a output tracking/termination synchronous pwm switcher with integrated fets ( swift?) tracks externally applied reference voltage as a member of the swift? family of dc/dc regu- lators, the tps54372 low-input voltage, high-output 60-m w mosfet switches for high efficiency current, synchronous-buck pwm converter integrates at 3-a continuous output source or sink all required active components. included on the current substrate with the listed features are a true, high 6% to 90% v i output tracking range performance, voltage error amplifier that enables wide pwm frequency: fixed 350 khz or maximum performance under transient conditions adjustable 280 khz to 700 khz and flexibility in choosing the output filter l and c components; an undervoltage-lockout circuit to pre- load protected by peak current limit and vent start-up until the input voltage reaches 3 v; an thermal shutdown internally and externally set slow-start circuit to limit integrated solution reduces board area and in-rush currents; and a status output to indicate valid total cost operating conditions. the tps54372 is available in a thermally enhanced 20-pin tssop (pwp) powerpad? package, which ddr memory termination voltage eliminates bulky heatsinks. ti provides evaluation active termination of gtl and sstl modules and the swift? designer software tool to high-speed logic families aid in quickly achieving high-performance power supply designs to meet aggressive equipment devel- dac controlled, high-current output stage opment cycles. precision point-of-load power supply simplified schematic please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. swift, powerpad are trademarks of texas instruments. production data information is current as of publication date. copyright ? 2002?2005, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. 6,4 mm x 6,6 mm t ypical size www .ti.com vin ph boot pgnd vsense vttq agnd vbias input tps54372 comp compensation network refin vddq t ? time ? 25 ms/div ? output v oltage ? 50 mv/div transient response v o ? output current ? 1 a/div i o v i = 5 v , v o = 1.25 v 0 a to 2.25 a simplified schema tic
absolute maximum ratings recommended operating conditions tps54372 slvs430d ? june 2002 ? revised february 2005 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. ordering information (1) t a refin voltage package part number (2) -40 c to 85 c 0.2 v to 1.75 v plastic htssop (pwp) tps54372pwp (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti website at www.ti.com . (2) the pwp package is also available taped and reeled. add an r suffix to the device type (i.e., tps54372pwpr). see the application section of the data sheet for powerpad drawing and layout information. over operating free-air temperature range unless otherwise noted (1) tps54372 units vin, ena ?0.3 to 7 rt ?0.3 to 6 input voltage range, v i v vsense, refin ?0.3 to 4 boot ?0.3 to 17 vbias, comp, status ?0.3 to 7 output voltage range, v o v ph ?0.6 to 6 ph internally limited source current, i o comp, vbias 6 ma ph 6 a sink current, i s comp 6 ma ena, status 10 voltage differential agnd to pgnd 0.3 v operating virtual junction temperature range, t j ?40 to 125 c storage temperature, t stg ?65 to 150 c lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 c (1) stresses beyond those listed under "absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. min nom max unit input voltage, v i 3 6 v operating junction temperature, t j ?40 125 c 2 www .ti.com
dissipation ratings (1) (2) electrical characteristics tps54372 slvs430d ? june 2002 ? revised february 2005 thermal impedance t a = 25 c t a = 70 c t a = 85 c package junction-to-ambient power rating power rating power rating 20-pin pwp with solder 26.0 c/w 3.85 w (3) 2.11 w 1.54 w 20-pin pwp without solder 57.5 c/w 1.73 w 0.96 w 0.69 w (1) for more information on the pwp package, see ti technical brief, literature number slma002. (2) test board conditions: a. 3-inch x 3-inch, 4 layers, thickness: 0.062-inch b. 1.5-oz. copper traces located on the top of the pcb c. 1.5-oz. copper ground plane on the bottom of the pcb d. ten thermal vias (see recommended land pattern in applications section of this data sheet) (3) maximum power dissipation may be limited by overcurrent protection. t j = ?40 c to 125 c, v i = 3 v to 6 v (unless otherwise noted) parameter test conditions min typ max unit supply voltage, vin vin input voltage range 3.0 6.0 v f s = 350 khz, rt open, ph pin open 6.2 9.60 i (q) quiescent current f s = 500 khz, rt = 100 k w , ph pin open 8.4 12.8 ma shutdown, ena = 0 v 1 1.4 undervoltage lockout start threshold voltage, uvlo 2.95 3.0 v stop threshold voltage, uvlo 2.70 2.80 v hysteresis voltage, uvlo 0.14 0.16 v rising and falling edge deglitch, uvlo (1) 2.5 s bias voltage output voltage, vbias i (vbias) = 0 2.70 2.80 2.90 v output current, vbias (2) 100 a regulation line regulation (1) (3) i l = 1.5 a, f s = 350 khz, t j = 85 c 0.07 %/v load regulation (1) (3) i l = 0 a to 3 a, f s = 350 khz, t j = 85 c 0.03 %/a oscillator internally set free-running frequency rt open 280 350 420 khz rt = 180 k w (1% resistor to agnd) (1) 252 280 308 externally set free-running frequency range rt = 100 k w (1% resistor to agnd) 460 500 540 khz rt = 68 k w (1% resistor to agnd) (1) 663 700 762 ramp valley (1) 0.75 v ramp amplitude (peak-to-peak) (1) 1 v minimum controllable on time (1) 200 ns maximum duty cycle (1) 90% error amplifier error amplifier open-loop voltage gain 1 k w comp to agnd (1) 90 110 db error amplifier unity gain bandwidth parallel 10 k w , 160 pf comp to agnd (1) 3 5 mhz error amplifier common mode input voltage powered by internal ldo (1) 0 vbias v range input bias current, vsense vsense = v ref 60 250 na output voltage slew rate (symmetric), 1.0 1.4 v/s comp (1) (1) specified by design (2) static resistive loads only (3) specified by the circuit used in figure 8 3 www .ti.com
tps54372 slvs430d ? june 2002 ? revised february 2005 electrical characteristics (continued) t j = ?40 c to 125 c, v i = 3 v to 6 v (unless otherwise noted) parameter test conditions min typ max unit pwm comparator pwm comparator propagation delay time, pwm comparator input to ph pin (excluding 10-mv overdrive (1) 70 85 ns dead time) slow-start/enable enable threshold voltage, ena 0.82 1.20 1.40 v enable hysteresis voltage, ena (1) 0.03 v falling edge deglitch, ena (1) 2.5 s internal slow-start time 2.6 3.35 4.1 ms status output saturation voltage, status i sink = 2.5 ma 0.18 0.30 v leakage current, status v i = 3.6 v 1 a current limit v i = 3 v (1) 4 6.5 current limit a v i = 6 v (1) 4.5 7.5 current limit leading edge blanking time (1) 100 ns current limit total response time (4) 200 ns thermal shutdown thermal shutdown trip point (4) 135 150 165 c thermal shutdown hysteresis (4) 10 c output power mosfets v i = 6 v (5) 59 88 r ds(on) power mosfet switches m w v i = 3 v (5) 85 136 (4) specified by design (5) matched mosfets low-side r ds(on) , and high-side r ds(on) production tested. 4 www .ti.com
tps54372 slvs430d ? june 2002 ? revised february 2005 httsop powerpad (top view) terminal functions terminal description name no. agnd 1 analog ground. return for compensation network/output divider, slow-start capacitor, vbias capacitor, and rt resistor. connect powerpad connection to agnd. boot 5 bootstrap output. 0.022-f to 0.1-f low-esr capacitor connected from boot to ph generates floating drive for the high-side fet driver. comp 3 error amplifier output. connect frequency compensation network from comp to vsense ena 19 enable input. logic high enables oscillator, pwm control and mosfet driver circuits. logic low disables operation and places device in a low quiescent current state. pgnd 11-13 power ground. high current return for the low-side driver and power mosfet. connect pgnd with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. a single-point connection to agnd is recommended. ph 6-10 phase input/output. junction of the internal high-side and low-side power mosfets, and output inductor. rt 20 frequency setting resistor input. connect a resistor from rt to agnd to set the switching frequency, f s . refin 18 external reference input. high impedance input to slow-start and error amplifier circuits. status 4 open-drain output. asserted low when vin < uvlo, vbias and internal reference are not settled or the internal shutdown signal is active. otherwise status is high. vbias 17 internal bias regulator output. supplies regulated voltage to internal circuitry. bypass vbias pin to agnd pin with a high quality, low-esr 0.1-f to 1.0-f ceramic capacitor. v in 14-16 input supply for the power mosfet switches and internal bias regulator. bypass vin pins to pgnd pins close to device package with a high-quality, low-esr 10-f ceramic capacitor. vsense 2 error amplifier inverting input. connect to output voltage compensation network/output divider. 5 www .ti.com 12 3 4 5 6 7 8 9 10 2019 18 17 16 15 14 13 12 1 1 agnd vsense comp st a tus boot phph ph ph ph r t enarefin vbias vin vin vin pgnd pgnd pgnd
tps54372 slvs430d ? june 2002 ? revised february 2005 internal block diagram 6 www .ti.com falling edge deglitch enable comparator 1.2 v 2.95 v hysteresis: 0.03 v 2.5 m s falling and rising edge deglitch 2.5 m s vin uvlo comparator hysteresis: 0.16 v slow-start (0.25 v/ms minimum) ? + error amplifier thermal shutdown 150 c shutdown ss _dis pwm comparator osc leading edge blanking 100 ns r q s adaptive dead-t ime and control logic shutdown 30 m w vin reg vbias vinboot vin ph l o u t c o pgnd st a tus agnd vbias ilim comparator vin v t t rt comp vsense ena tps54672 30 m w ss _dis refin vddq
typical characteristics tps54372 slvs430d ? june 2002 ? revised february 2005 drain-source drain-source internally set on-state resistance on-state resistance ocillator frequency vs vs vs junction temperature junction temperature junction temperature figure 1. figure 2. figure 3. externally set ocillator frequency device power losses internal slow-start time vs vs vs junction temperature load current junction temperature figure 4. figure 5. figure 6. error amplifier open-loop response figure 7. 7 250 350 450 550 650 750 ?40 0 25 85 125 t j ? junction t emperature ? c f ? internally set oscillator frequency ? khz rt = open 0 10 20 30 40 50 60 70 80 90 ?40 0 25 85 125 vin = 5 vi o = 3 a t j ? junction t emperature ? c drain source on-state reststance ? m w 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 0 1 2 3 4 i l ? load current ? a device power losses ? w t j ? 125 c f s = 700 khz v i = 3.3 v v i = 5 v www .ti.com 200 300 400 500 600 700 800 ?40 0 25 85 125 t j ? junction t emperature ? c f ? externally set oscillator frequency ? khz rt = 68 k w rt = 100 k w rt = 180 k w 2.75 2.90 3.05 3.20 3.35 3.50 3.65 ?40 0 25 85 125 t j ? junction t emperature ? c internal slow-start time ? ms 3.80 ?20 0 20 40 60 80 100 120 140 1 100 1 k 1 m ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 10 k 100 k 10 m f ? frequency ? hz gain ? db phase ? degrees phase gain r l = 10 k w , c l = 160 pf , t a = 25 c 0 20 40 60 80 100 120 ?40 0 25 85 125 vin = 3.3 vi o = 3 a drain source on-state reststance ? m w t j ? junction t emperature ? c
application information typical circuit input voltage component selection feedback circuit tps54372 slvs430d ? june 2002 ? revised february 2005 figure 8. application circuit figure 8 shows the schematic diagram for a typical the input voltage is a nominal 3.3 or 5.0 vdc. the tps54372 application. the tps54372 (u1) can pro- input filter (c4) is a 10-f ceramic capacitor (taiyo vide up to 3 a of output current at a nominal output yuden). capacitor c8, a 10-f ceramic capacitor voltage of one half of v ddq (typically 1.25 v). for (taiyo yuden) that provides high-frequency decoup- proper operation, the powerpad underneath the ling of the tps54372 from the input supply, must be integrated circuit tps54372 is soldered directly to the located as close as possible to the device. ripple printed-circuit board. current is carried in both c4 and c8, and the return path to pgnd should avoid the current circulating in the output capacitors c7, c10, and c11. the values for the components used in this design example were selected for good transient response and small pcb area. special polymer capacitors are the values for these components are selected to used in the output filter circuit. a small size, small provide fast transient response times. components value output inductor is also used. compensation r1, r2, r3, c1, c2, and c3 form the loop compen- network components are chosen to maximize sation network for the circuit. for this design, a closed-loop bandwidth and provide good transient type-3 topology is used. the transfer function of the response characteristics. additional design infor- feedback network is chosen to provide maximum mation is available at www.ti.com. closed-loop gain available with open-loop character- istics of the internal error amplifier. closed-loop crossover frequency is typically between 80 khz and 125 khz for input from 3 v to 6 v. 8 www .ti.com j2 + + j1 2 1 v i gnd tp1 c410 m f tp2 tp3 u1 tps54372pwp 2019 18 17 16 15 14 1312 1 1 12 3 4 5 6 78 9 10 agndvsense comp st a tus bootph ph ph ph ph pwrp ad 21 rt ena refinvbias vinvin vin pgndpgnd pgnd r2 36.5 k w c2 470 pf c1 12 pf c6 0.047 pf r110 k w r31.21 k w c31500 pf tp4 r42.4 w c53300 pf l1 1 m h 1 2 c7150 m f c10150 m f c1 1 1 m f tp5tp6 tp7 12 vttqgnd tp8 c810 m f c91 m f r571.5 k w r710 k w c120.1 m f c130.1 m f r610 k w tp9 j2 12 vddqgnd
operating frequency output filter pcb layout layout considerations for thermal tps54372 slvs430d ? june 2002 ? revised february 2005 separate wide trace for the analog ground signal path. this analog ground should be used for the in the application circuit, rt is grounded through a voltage set-point divider, timing resistor rt, and bias 71.5-k w resistor to select the operating frequency of capacitor grounds. connect this trace directly to 700 khz. to set a different frequency, place a 68-k w agnd (pin 1). to 180-k w resistor between rt (pin 20) and analog ground or leave rt floating to select the default of the ph pins should be tied together and routed to 350 khz. the resistance can be approximated using the output inductor. because the ph connection is the following equation: the switching node, the inductor should be located close to the ph pins, and the area of the pcb conductor minimized to prevent excessive capacitive coupling. connect the boot capacitor between the phase node and the boot pin as shown. keep the boot capacitor the output filter is composed of a 1.0-h inductor close to the ic and minimize the conductor trace and two 150-f capacitors. the inductor is a low dc lengths. connect the output filter capacitor(s) as resistance (0.010 w ) type, vishay ihlp-2525cz-01 shown, between the vout trace and pgnd. it is 1.0-h, 8.5-a rated dc output. the capacitors used important to keep the loop formed by the ph pins, are 150-f, 6.3-v special polymer types. lout, cout, and pgnd as small as practical. place the compensation components from the vout trace to the vsense and comp pins. do not place figure 9 shows a generalized pcb layout guide for these components too close to the ph trace. due to the tps54372. the size of the ic package and the device pinout, they have to be routed somewhat close, but maintain the vin pins should be connected together on the as much separation as possible while still keeping the printed-circuit board (pcb) and bypassed with a layout compact. low-esr ceramic bypass capacitor. care should be taken to minimize the loop area formed by the bypass connect the bias capacitor from the vbias pin to capacitor connections, the vin pins, and the analog ground using the isolated analog ground tps54372 ground pins. the minimum recommended trace. if an rt resistor is used, connect it to this trace bypass capacitance is 10-f ceramic with a x5r- or as well. x7r-grade dielectric, and the optimum placement is closest to the vin pins and the pgnd pins. performance the tps54372 has two internal grounds (analog and power). inside the tps54372, the analog ground ties for operation at full rated load current, the analog to all of the noise-sensitive signals, while the power ground plane must provide adequate heat dissipating ground ties to the noisier power signals. noise area. a 3-inch by 3-inch plane of 1-ounce copper is injected between the two grounds can degrade the recommended, though not mandatory, depending on performance of the tps54372, particularly at higher ambient temperature and airflow. most applications output currents. ground noise on an analog ground have larger areas of internal ground plane available, plane can also cause problems with some of the and the powerpad should be connected to the control and bias signals. for these reasons, separate largest area available. additional areas on the top or analog and power ground traces are recommended. bottom layers also help dissipate heat, and any area there should be an area of ground on the top layer available should be used when 3-a or greater oper- directly under the ic, with an exposed area for ation is desired. connection from the exposed area of connection to the powerpad. use vias to connect the powerpad to the analog ground plane layer this ground area to any internal ground planes. use should be made using 0.013-inch diameter vias to additional vias at the ground side of the input and avoid solder wicking through the vias. six vias should output filter capacitors as well. the agnd and pgnd be in the powerpad area with four additional vias pins should be tied to the pcb ground by connecting located under the device package. the size of the them to the ground area under the device as shown. vias under the package, but not in the exposed the only components that should tie directly to the thermal pad area, can be increased to 0.018 inch. power ground plane are the input capacitors, the additional vias beyond the ten recommended that output capacitors, the input voltage decoupling ca- enhance thermal performance should be included in pacitor, and the pgnd pins of the tps54372. use a areas not under the device package. 9 r 5 0 0 k h z s w i t c h i n g f r e q u e n c y 1 0 0 [ k ] www .ti.com
performance graphs tps54372 slvs430d ? june 2002 ? revised february 2005 figure 9. pcb layout for 20-pin pwp powerpad efficiency load regulation vs vs output current output current figure 10. figure 11. 10 agnd boot vsense comp pwrgd phph ph ph ph r t ena refin vbias vin vin vin pgndpgnd pgnd vout ph v in t opside ground area via to ground plane analog ground trace exposed compensa tion network output induct or outputfil ter cap acit or bootcap acit or inputbyp ass cap acit or inputbulk fil ter resist or divider network bias cap acit or tracking vol t age powerp ad area 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 efficiency ? % i o ? output current ? a f s = 700 khz, v i = 5 v , v o = 1.25 v 1.245 1.247 1.249 1.251 1.253 1.255 0 1 2 3 4 i o ? output current ? a load regulation f s = 700 khz, t a = 25 c, v i = 5 v , v o = 1.25 v www .ti.com
tps54372 slvs430d ? june 2002 ? revised february 2005 performance graphs (continued) line regulation vs input voltage output ripple voltage figure 12. figure 13. transient response slow-start timing figure 14. figure 15. ambient temperature source-sink vs transient response load current (1) figure 16. (1) safe operating area is applicable to the test board conditions listed in the dissipation rating table section of this data sheet. figure 17. 11 t ? time ? 1 m s/div output ripple v oltage ? 10 mv/div f s = 700 khz, i o = 3 a, v i = 5 v , v o = 1.25 v 1.247 1.248 1.249 1.25 1.251 1.252 1.253 3 4 5 6 i o = 3 a v i ? input v oltage ? v line regulation i o = 0 a f s = 700 khz, t a = 25 c, v o = 1.25 v i o = 1.5 a www .ti.com t ? time ? 25 ms/div ? output v oltage ? 50 mv/div v o ? output current ? 1 a/div i o v i = 5 v , v o = 1.25 v 0 a to 2.25 a v i = 5 v , v o = 1.25 v t ?time ? 2.5 ms/div ? input v oltage ? 2 v/div v i ? output v oltage ? 500 mv/div v o t ? time ? 100 m s/div ? output v oltage ? 50 mv/div v o ? output current ? 1 a/div i o v i = 5 v , v o = 1.25 v ?1.5 a to 1.5 a 25 35 45 55 65 75 85 95 105 1 15 125 0 1 2 3 4 ? ambient t emperature ? i l ? load current ? a c t a safe operating area v i = 3.3 v v i = 5 v t a = 25 c, v o = 1.25 v (see note)
detailed description undervoltage lockout (uvlo) voltage reference oscillator and pwm ramp enable (ena) slow-start error amplifier pwm control vbias regulator (vbias) tps54372 slvs430d ? june 2002 ? revised february 2005 the tps54372 incorporates an undervoltage lockout the refin pin provides an input for a user supplied circuit to keep the device disabled when the input tracking voltage. typically this input is one half of voltage (vin) is insufficient. during power up, internal v ddq . the input range for this external reference is circuits are held inactive until vin exceeds the 0.2 v to 1.75 v. above this level, the internal nominal uvlo threshold voltage of 2.95 v. once the bandgap reference overrides the externally supplied uvlo start threshold is reached, device start-up reference voltage. begins. the device operates until vin falls below the nominal uvlo comparator. hysteresis in the uvlo comparator, and a 2.5-s rising and falling edge the oscillator frequency can be set to an internally deglitch circuit reduce the likelihood of shutting the fixed value of 350 khz by leaving the rt pin device down due to noise on vin. unconnected (floating). if a different frequency of operation is required for the application, the oscillator frequency can be externally adjusted from 280 to 700 the enable pin, ena, provides a digital control to khz by connecting a resistor to the rt pin to ground. enable or disable (shutdown) the tps54372. an input the switching frequency is approximated by the voltage of 1.4 v or greater ensures the tps54372 is following equation, where r is the resistance from rt enabled. an input of 0.82 v or less ensures the to agnd: device operation is disabled. these are not standard logic thresholds, even though they are compatible with ttl outputs. the following table summarizes the frequency selec- when ena is low, the oscillator, slow-start, pwm tion configurations: control and mosfet drivers are disabled and held in an initial state ready for device start-up. on an ena frequency selection transition from low to high, device start-up begins with switching frequency rt pin the output starting from 0 v. 350 khz, internally set float externally set 280 khz to 700 khz r = 180 k w to 68 k w the slow-start circuit provides start-up slope control of the output voltage to limit in-rush currents. the nominal internal slow-start rate is 0.25 v/ms with the the high-performance, wide bandwidth, voltage error minimum rate being 0.35 v/ms. when the voltage on amplifier sets the tps54372 apart from most dc/dc refin rises faster than the internal slope or is converters. the user has a wide range of output l present when device operation is enabled, the output and c filter components to suit the particular appli- rises at the internal rate. if the reference voltage on cation needs. type-2 or type-3 compensation can be refin rises more slowly, then the output rises at employed using external compensation components. approximately the same rate as refin. signals from the error amplifier output, oscillator, and the vbias regulator provides internal analog and current limit circuit are processed by the pwm control digital blocks with a stable supply voltage over logic. referring to the internal block diagram, the variations in junction temperature and input voltage. a control logic includes the pwm comparator, or gate, high quality, low-esr, ceramic bypass capacitor is pwm latch, and portions of the adaptive dead-time required on the vbias pin. x7r- or x5r-grade and control logic block. during steady-state operation dielectrics are recommended because their values below the current limit threshold, the pwm are more stable over temperature. the bypass ca- comparator output and oscillator pulse train alter- pacitor should be placed close to the vbias pin and nately reset and set the pwm latch. once the pwm returned to agnd. external loading on vbias is latch is set, the low-side fet remains on for a allowed, with the caution that internal circuits require minimum duration set by the oscillator pulse width. a minimum vbias of 2.7 v, and external loads on during this period, the pwm ramp discharges rapidly vbias with ac or digital switching noise may degrade to its valley voltage. when the ramp begins to charge performance. the vbias pin may be useful as a back up, the low-side fet turns off and high-side reference voltage for external circuits. fet turns on. as the pwm ramp voltage exceeds the 12 www .ti.com s w i t c h i n g f r e q u e n c y 1 0 0 k r 5 0 0 [ k h z ]
overcurrent protection thermal shutdown dead-time control and mosfet status tps54372 slvs430d ? june 2002 ? revised february 2005 error amplifier output voltage, the pwm comparator resets the latch, thus turning off the high-side fet the cycle by cycle current limiting is achieved by and turning on the low-side fet. the low-side fet sensing the current flowing through the high-side remains on until the next oscillator pulse discharges mosfet and comparing this signal to a preset the pwm ramp. overcurrent threshold. the high-side mosfet is during transient conditions, the error amplifier output turned off within 200 ns of reaching the current limit could be below the pwm ramp valley voltage or threshold. a 100-ns leading edge blanking circuit above the pwm peak voltage. if the error amplifier is prevents false tripping of the current limit when the high, the pwm latch is never reset and the high-side high-side switch is turning on. current limit detection fet remains on until the oscillator pulse signals the occurs only when current flows from vin to ph when control logic to turn the high-side fet off and the sourcing current to the output filter. load protection low-side fet on. the device operates at its maxi- during current sink operation is provided by thermal mum duty cycle until the output voltage rises to the shutdown. regulation set-point, setting vsense to approxi- mately the same voltage as vref. if the error amplifier output is low, the pwm latch is continually the device uses the thermal shutdown to turn off the reset and the high-side fet does not turn on. the power mosfets and disable the controller if the low-side fet remains on until the vsense voltage junction temperature exceeds 150 c. the device is decreases to a range that allows the pwm released from shutdown automatically when the junc- comparator to change states. the tps54372 is tion temperature decreases to 10 c below the ther- capable of sinking current continuously until the mal shutdown trip-point, and starts up under control output reaches the regulation set-point. of the slow-start circuit. if the current limit comparator trips for longer than thermal shutdown provides protection when an over- 100 ns, the pwm latch resets before the pwm ramp load condition is sustained for several milliseconds. exceeds the error amplifier output. the high-side fet with a persistent fault condition, the device cycles turns off and low-side fet turns on to decrease the continuously; starting up by control of the soft-start energy in the output inductor and consequently the circuit, heating up due to the fault condition, and then output current. this process is repeated each cycle in shutting down on reaching the thermal limit trip-point. which the current limit comparator is tripped. this sequence repeats until the fault condition is removed. drivers adaptive dead-time control prevents shoot-through the status pin is an open-drain output that indicates current from flowing in both n-channel power when internal conditions are sufficient for proper mosfets during the switching transitions by actively operation. status can be coupled back to a system controlling the turnon times of the mosfet drivers. controller or monitor circuit to indicate that the termin- the high-side driver does not turn on until the gate ation or tracking regulator is ready for start-up. drive voltage to the low-side fet is below 2 v, while status is high impedance when the tps54372 is the low-side driver does not turn on until the voltage operating or ready to be enabled. at the gate of the high-side mosfet is below 2 v. the high-side and low-side drivers are designed with status is active low if any of the following occur: 300-ma source and sink capability to quickly drive the vin < uvlo threshold power mosfets gates. the low-side driver is sup- vbias or internal reference have not settled. plied from vin, while the high-side drive is supplied thermal shutdown is active. from the boot pin. a bootstrap circuit uses an external boot capacitor and an internal 2.5- w . bootstrap switch connected between the vin and boot pins. the integrated bootstrap switch improves drive efficiency and reduces external component count. 13 www .ti.com
package option addendum www.ti.com 11-apr-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples tps54372pwp active htssop pwp 20 70 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 tps54372 tps54372pwpg4 active htssop pwp 20 70 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 tps54372 tps54372pwpr active htssop pwp 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 tps54372 TPS54372PWPRG4 active htssop pwp 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 tps54372 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) multiple top-side markings will be inside parentheses. only one top-side marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire top-side marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 11-apr-2013 addendum-page 2 other qualified versions of tps54372 : ? automotive: tps54372-q1 note: qualified version definitions: ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps54372pwpr htssop pwp 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 q1 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tps54372pwpr htssop pwp 20 2000 367.0 367.0 38.0 package materials information www.ti.com 14-jul-2012 pack materials-page 2

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all semiconductor products (also referred to herein as ? components ? ) are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in ti ? s terms and conditions of sale of semiconductor products. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. ti assumes no liability for applications assistance or the design of buyers ? products. buyers are responsible for their products and applications using ti components. to minimize the risks associated with buyers ? products and applications, buyers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti components or services are used. information published by ti regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of significant portions of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti components or services with statements different from or beyond the parameters stated by ti for that component or service voids all express and any implied warranties for the associated ti component or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of ti components in its applications, notwithstanding any applications-related information or support that may be provided by ti. buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. buyer will fully indemnify ti and its representatives against any damages arising out of the use of any ti components in safety-critical applications. in some cases, ti components may be promoted specifically to facilitate safety-related applications. with such components, ti ? s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. nonetheless, such components are subject to these terms. no ti components are authorized for use in fda class iii (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. only those ti components which ti has specifically designated as military grade or ? enhanced plastic ? are designed and intended for use in military/aerospace applications or environments. buyer acknowledges and agrees that any military or aerospace use of ti components which have not been so designated is solely at the buyer ' s risk, and that buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti has specifically designated certain components as meeting iso/ts16949 requirements, mainly for automotive use. in any case of use of non-designated products, ti will not be responsible for any failure to meet iso/ts16949. products applications audio www.ti.com/audio automotive and transportation www.ti.com/automotive amplifiers amplifier.ti.com communications and telecom www.ti.com/communications data converters dataconverter.ti.com computers and peripherals www.ti.com/computers dlp ? products www.dlp.com consumer electronics www.ti.com/consumer-apps dsp dsp.ti.com energy and lighting www.ti.com/energy clocks and timers www.ti.com/clocks industrial www.ti.com/industrial interface interface.ti.com medical www.ti.com/medical logic logic.ti.com security www.ti.com/security power mgmt power.ti.com space, avionics and defense www.ti.com/space-avionics-defense microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com omap applications processors www.ti.com/omap ti e2e community e2e.ti.com wireless connectivity www.ti.com/wirelessconnectivity mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2016, texas instruments incorporated

▲Up To Search▲

Price & Availability of TPS54372PWPRG4

	To Download TPS54372PWPRG4 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .